Currently when making semiconductor structures with three dimensional FinFETs, the standard is to form the fin early in the fabrication process; generally before well ion implants. However, early fin reveal can cause a multitude of subsequent issues. For example, increased structure topology resulting from the early fin reveal makes gate formation difficult because of various patterning levels. This topology variation may lead to dummy poly fill voids and defects between fins. In the future, FinFETs with smaller FIN pitch will likely be needed for increased performance leading to exasperated complications if the fins are revealed early in structure fabrication.